This invention pertains to a method and apparatus for allowing a large amount of digital data to be transferred over a bus without losing real-time control over peripheral devices during data transfer.
Every input-output card in a minicomputer system must communicate its control signal and its data transfers on a single host computer bus. In conventional systems, if large quantities of data must be transferred to a particular destination, data transfer blocks out the direct or real-time control of any peripheral device that is coupled to the bus during the time that the large block of data is being transferred.
One prior art method used to detect the status of and maintain control over devices subject to real-time control is to transfer small blocks of data with predefined open time intervals between blocks so that the computer can regain control over any peripheral device repeatedly during the open time intervals. Control action and status determination is usually not necessary at the predefined time intervals between all of the data blocks. Thus, intervals between data blocks become system dead time. In addition, this prior art method does not allow true real-time control over peripheral devices, requires counting and timing circuitry, and does not use the full bandwidth of the peripheral bus.
A second prior art method for direct data transfer that actually allows uninterrupted real-time control, requires use of two host bus interface circuits. One circuit communicates only with the control circuitry and the other with the direct transfer circuitry and the memory circuitry. This method not only requires two separate costly and space consuming bus structures but also requires twice as much host bus interface circuitry as the previously discussed prior art method. However, large quantities of data can be transferred continuously in blocks of any length. The control circuitry can also maintain control and status checking during data transfer and the peripheral bus can be used to its full bandwidth.